CS4398-CZZ【PDF 19/46 页】IC DAC 120DB 192KHZ W/VC 28TSSOP

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DS568F1

CS4398

5.4.1

Writing in IC Format

To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the

chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Mem-

ory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by

the data to be written. To write multiple registers, continue providing a clock and data, waiting for the

CS4398 to acknowledge between each byte. To end the transaction, send a STOP condition.

5.4.2

Reading in IC Format

To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the

chip address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the reg-

ister pointed to by the MAP will be output after the chip address. To read multiple registers, continue pro-

viding a clock and issue an ACK after each byte. To end the transaction, send a STOP condition.

5.5

SPI Format

In SPI format, CS is the CS4398 chip select signal; CCLK is the Control Port bit clock; CDIN is the input

data line from the microcontroller; CDOUT is the output data line and the chip address is 1001100. CS,

CCLK,and CDIN are all inputs, and data is clocked in on the rising edge of CCLK. CDOUT is an output and

is high-impedance when not actively outputting data.

5.5.1

Writing in SPI

Figure 15 shows the operation of the Control Port in SPI format. To write to a register, bring CS low. The

first seven bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write indi-

cator (R/W), which must be low to write. The next eight bits form the Memory Address Pointer (MAP),

which is set to the address of the register that is to be updated. The next eight bits are the data that will

be placed into register designated by the MAP. To write multiple registers, keep CS low and continue pro-

viding clocks on CCLK. End the read transaction by setting CS high.

SD A

SC L

100 1 1

AD 1

R/W

Sta rt

AC K

DA T A

1-8

AC K

DAT A

1-8

ACK

Sto p

N o te : If o peratio n is a w rite, th is byte contain s th e M em o ry A ddress P o inter, M A P .

No te 1

AD 0

Figure 14. Control Port Timing, IC Format

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